A programmable logic device, sometimes referred to as programmable application specific integrated circuit (PASIC), field programmable gate array, or complex programmable logic device (CPLD), is a versatile integrated circuit chip, the internal circuitry of which may be configured by an individual user to realize a user-specific circuit. To configure a programmable logic device, the user configures an on-chip interconnect structure of the programmable logic device so that selected input terminals and selected output terminals of selected on-chip circuit components are electrically connected together in such a way that the resulting circuit is the specific circuit desired by the user.
Programmable logic devices include a number of programmable logic blocks that are interconnected by a programmable routing network, sometimes referred to as a programmable interconnect. A logic block may be comprised of one or more logic cells, wherein a logic cell, in general, is made up of one or more logic elements with a defined number of inputs and outputs coupled to the routing network. For example, a logic cell, the core unit of a logic block, may include a combination of lookup tables (LUTs) and registers, that receives input signals from the routing network, as well as produce output signals to the routing network. During configuration of the programmable logic device, the truth table for each lookup table is programmed to implement a desired logical function.
FIG. 1, by way of example, illustrates a conventional logic cell 10, which includes two LUTs 12, 14, a multiplexor 16 and a register 18. Each LUT 12, 14 receives four inputs from a routing network (not shown). The combinatorial outputs 12a, 14a of each LUT 12, 14 may be provided as a direct output of the logic cell 10, and are also received by multiplexor 16. The multiplexor 16 further receives a third input Data Input from the routing network. The multiplexor 16 selects from the combinatorial outputs 12a, 14a, and Data Input to provide an output signal that is received by register 18. The selection by multiplexor 16 may be fixed, e.g., based on the initial programming of the programmable logic device to a tie high (VDD) signal or a tie low (GND) signal, or may be dynamic, which requires two additional resources from the routing network. The register 18 receives a clock signal from the routing network, as well as other control signals (e.g., SET, RESET) and produces an output signal 18a, which may be provided as an output of the logic cell 10.
There is a desire in the art for improved programmable logic block architectures that provide a more efficient use of routing resources and power.